MOSFET Exploration 2_N-MOSFET DC Biasing and CS Amp Configurations

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University of California, Berkeley *

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210

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Electrical Engineering

Date

Feb 20, 2024

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docx

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4

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MOSFET Exploration 2 N-MOSFET DC Biasing and Common-Source Amplifier Configurations: Part I: N-MOSFET DC Biasing Figure 1: N-MOSFET DC Bias Circuit 1. DC Bias Circuit Design: A. Design the NMOS DC Bias Circuit of Figure 1: that is, determine the values of R D and R S so that the transistor operates at I D = 11 mA and V D = + 2.5 V . The NMOS transistor has V tn = 2.1 V, k n = 132 mA/V 2 . (These are typical values for a BS170 transistor and should be similar to the values that you measured in MOSFET Exploration 1). Neglect the channel length modulation effect (i.e. assume that λ = 0 ). (NOTE: The MOSFET transconductance process parameter , k n ≡k n ' W L ). Outline each step of your design process and summarize your results in Table 1. (Reference: See Example 5.3 in the Sedra and Smith textbook, 7 th ed.). Include in Table 1 the standard 5% tolerance resistor values that are closest to your design values. Table 1: NMOS DC Bias Circuit Design R D R S Resistor value from design Closest Standard 5% tol.
Resistor value B. Design Validation with Multisim Live Simulation: In Multisim Live create the design of the circuit of Figure 1 using the closest standard 5% tolerance resistor values for of R D and R S and the Multisim 2N7000 NMOS model component. Insert voltage probes at nodes D and S and perform a DC Op (DC Operating Point) simulation to determine the simulated values of V D and V S . Calculate the value of I D and complete Table 2 to compare the DC Bias Point specifications in 1. A to what was achieved in the simulated circuit. Table 2 Validation of DC Bias Circuit Design V D V S I D Design Specification 2.5 V 11 mA Design Validation from Simulation Part II: Common-Source Amplifier Configurations Figure 2: NMOS Common-Source Amplifier Configurations 2. Theory:
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